Who needs real hardware?
One of the very nice things you can do with Verilog (and VHDL), is to use it as basis for a simulator. Especially with synchronous designs, which do all their work in lock-step with a central clock, simulators can provide a good insight into what’s going on without having to load the design onto real silicon.
Verilator is a great tool for this, and does something really clever: the Verilog code is first translated into C++, which you then include in a small main loop of your own, compile, and run - preferably on a modern laptop or desktop machine.
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