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Water damage
We recently had a small water leak in the kitchen - leading to a 3-hour server outage for JeeLabs. Very early in the morning, so very few people will have noticed it - other than an ever-vigilant...
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Going 32-bit, at last
Given last week’s mishap, and the resulting damage to the main metering JeeNode, it’s time to start creating a new setup. While I’m at it, I’ll throw a few new measurements into the mix and will also...
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Upstairs, downstairs
It turns out that tinkering and development is hard when the signals to be measured are located far from my desk and electronics workbench. The meter cabinet is located downstairs next to the front...
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This week's potpourri
This week will be a hodgepodge of topics which I’ve been working on recently: a hardware interaction which kept me really puzzled for quite some time, a delightful excursion into the deeper innards of...
View ArticleWorking on JEM
The JeeLabs Energy Monitor prototype is progressing nicely - once I figured out that I had my numbering of the Arduino analog pins 0..5 reversed… doh!Here is what’s on the menu for this week:Tracking...
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Tying up several loose ends
This week is yet another mixed bag of topics, all related to either the JeeLabs Energy Monitor, or taking the STM32F103 platform further with Mecrisp Forth.It might not look like much from afar, but...
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Standalone USB firmware
Announcement: As of today, the JeeLabs weblog is switching into lower gear, as we move towards the Northern hemisphere’s summer recess. Instead of a weekly post plus several articles, there will be...
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Thoughts about app structure
These are some ideas about how to structure the flash and RAM memory for applications built on top of Mecrisp Forth.First off: 64 KB of flash memory turns out to be plenty for very substantial...
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Forth on Nandland Go Board
After a recent excursion into FPGAs, and in particular Z80 + CP/M emulation, I’ve been tracking developments and keeping tabs on what’s being going on in both FPGA- and Retrocomputing-land.FPGAs are...
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Convolution, anyone?
Right now, the JeeLabs Energy Monitor only tracks and reports three mains pulse counters here at JeeLabs. The smart meter’s P1 serial data source will be added soon, but there have been issues with...
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Keeping track of time
One of the things I’d love to do is measure the AC mains grid frequency with fairly high precision. We know that it’s kept at 50 Hz long term, so that old mains-powered alarm clocks, etc. can keep...
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Mecrisp on other platforms
We’ve already seen that Mecrisp Forth is also available for the Nandland Go Board FPGA board.But Mecrisp Forth can in fact be used on several other platforms.For one, there’s the MSP430 version (which...
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Scandinavia by rail
It will not have been obvious from this weblog, since new posts are now automatically published each Wednesday at midnight, but these past few weeks I’ve been on vacation, travelling across Germany,...
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The disconnected life
On those recent travels across Scandinavia, I had a chance to reset my expectations of what life is like when not “attached to internet” all the time. Quite unlike what I’d imagined, I can tell...
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TFoC: FPGA & Forth = VGA
(This article is part of the The Fabric of Computing series: in search of simplicity)Here is a fun project, created from start to finish by Matthias Koch, as part of his Mecrisp implementation of...
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CPLDs and FPGAs
It’s vacation time - I’m having fun doodling with logic devices and gate arrays… have been messing about with them before, when duplicating Grant Searle’s neat Z80 setup.This time I want to write some...
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VGA in Verilog
Verilog is a Hardware Description Language - you can “write” logic circuits in it. It’s very intriguing due to it’s built-in parallelism and the way an actual circuit can be inferred from a high-level...
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Sweep, staircase, and blanking
We’ve all seen images like this before:Well, maybe not consciously, but this is the way images are “painted” across the screen of a CRT in old TVs. A sweep from left to right, combined with a step-wise...
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PMOD connectors
Last week’s post used the 12-pin “Pmod” connector on my FPGA board to generate the X, Y, and Z signals.Pmod™ is a simple header pinout standard (PDF) defined by Digilent. There’s a (free) license for...
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Let's build (half a) UART
The problem with FPGAs is that they’re so low-level. It’s a bit like sitting on the floor with a huge pile of 7400 series chips, trying to make them do something … u s e f u l ?When starting from...
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